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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TRCSYNCPR, Synchronization Period Register</h1><p>The TRCSYNCPR characteristics are:</p><h2>Purpose</h2>
        <p>Controls how often trace protocol synchronization requests occur.</p>
      <h2>Configuration</h2><p>External register TRCSYNCPR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-trcsyncpr.html">TRCSYNCPR[31:0]</a>.</p><p>This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCSYNCPR are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>TRCSYNCPR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="27"><a href="#fieldset_0-31_5">RES0</a></td><td class="lr" colspan="5"><a href="#fieldset_0-4_0">PERIOD</a></td></tr></tbody></table><h4 id="fieldset_0-31_5">Bits [31:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_0">PERIOD, bits [4:0]</h4><div class="field">
      <p>Defines the number of bytes of trace between each periodic trace protocol synchronization request.</p>
    <table class="valuetable"><tr><th>PERIOD</th><th>Meaning</th></tr><tr><td class="bitfield">0b00000</td><td>
          <p>Trace protocol synchronization is disabled.</p>
        </td></tr><tr><td class="bitfield">0b01000</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>8</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b01001</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>9</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b01010</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>10</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b01011</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>11</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b01100</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>12</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b01101</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>13</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b01110</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>14</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b01111</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>15</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b10000</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>16</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b10001</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>17</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b10010</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>18</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b10011</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>19</sup> bytes of trace.</p>
        </td></tr><tr><td class="bitfield">0b10100</td><td>
          <p>Trace protocol synchronization request occurs after 2<sup>20</sup> bytes of trace.</p>
        </td></tr></table><p>Other values are reserved. If a reserved value is programmed into PERIOD, then the behavior of the synchronization period counter is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> and one of the following behaviors occurs:</p>
<ul>
<li>No trace protocol synchronization requests are generated by this counter.
</li><li>Trace protocol synchronization requests occur at the specified period.
</li><li>Trace protocol synchronization requests occur at some other <span class="arm-defined-word">UNKNOWN</span> period which can vary.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing TRCSYNCPR</h2>
        <p>Must be programmed if <a href="ext-trcidr3.html">TRCIDR3</a>.SYNCPR == 0.</p>

      
        <p>Writes are <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> if the trace unit is not in the Idle state.</p>
      <h4>TRCSYNCPR can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>ETE</td><td><span class="hexnumber">0x034</span></td><td>TRCSYNCPR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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